  |
TRON VLSI CPU - http://tronweb.super-nova.co.jp/tronvlsicpu.html
CISC 32-bit processor architecture developed to serve as main hardware building block of the realtime TRON Hypernetwork (Highly Functional Distributed System: HFDS), the ultimate goal of the TRON Project. |
 |
A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming - http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/1989/03/m3toc.xml&DOI=10.1109/40.31476
Abstract of paper on Gmicro/FPU (floating-point unit), defines 23 coprocessor instructions; with references, purchase option. [IEEE Micro] |
| |
The Gmicro/100 32-Bit Microprocessor - http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/1991/04/m4toc.xml&DOI=10.1109/40.85722
Abstract of paper on Gmicro/100, 32-bit CISC VLSI, based on TRON specification; with references, purchase option. [IEEE Micro] |
| |
The Gmicro/500 Superscalar Microprocessor with Branch Buffers - http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/1993/05/m5toc.xml&DOI=10.1109/40.237998
Abstract of paper on Gmicro/500, with RISC-like dual-pipeline structure to execute basic instructions fast, upward-object-compatible with earlier Gmicro variants; with references, purchase option. [IEEE Micro] |